diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h
new file mode 100644
index 0000000..450784c
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32h7/gpio.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+#include <asm/gpio.h>
+
+enum stm32_gpio_port {
+	STM32_GPIO_PORT_A = 0,
+	STM32_GPIO_PORT_B,
+	STM32_GPIO_PORT_C,
+	STM32_GPIO_PORT_D,
+	STM32_GPIO_PORT_E,
+	STM32_GPIO_PORT_F,
+	STM32_GPIO_PORT_G,
+	STM32_GPIO_PORT_H,
+	STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+	STM32_GPIO_PIN_0 = 0,
+	STM32_GPIO_PIN_1,
+	STM32_GPIO_PIN_2,
+	STM32_GPIO_PIN_3,
+	STM32_GPIO_PIN_4,
+	STM32_GPIO_PIN_5,
+	STM32_GPIO_PIN_6,
+	STM32_GPIO_PIN_7,
+	STM32_GPIO_PIN_8,
+	STM32_GPIO_PIN_9,
+	STM32_GPIO_PIN_10,
+	STM32_GPIO_PIN_11,
+	STM32_GPIO_PIN_12,
+	STM32_GPIO_PIN_13,
+	STM32_GPIO_PIN_14,
+	STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+	STM32_GPIO_MODE_IN = 0,
+	STM32_GPIO_MODE_OUT,
+	STM32_GPIO_MODE_AF,
+	STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+	STM32_GPIO_OTYPE_PP = 0,
+	STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+	STM32_GPIO_SPEED_2M = 0,
+	STM32_GPIO_SPEED_25M,
+	STM32_GPIO_SPEED_50M,
+	STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+	STM32_GPIO_PUPD_NO = 0,
+	STM32_GPIO_PUPD_UP,
+	STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+	STM32_GPIO_AF0 = 0,
+	STM32_GPIO_AF1,
+	STM32_GPIO_AF2,
+	STM32_GPIO_AF3,
+	STM32_GPIO_AF4,
+	STM32_GPIO_AF5,
+	STM32_GPIO_AF6,
+	STM32_GPIO_AF7,
+	STM32_GPIO_AF8,
+	STM32_GPIO_AF9,
+	STM32_GPIO_AF10,
+	STM32_GPIO_AF11,
+	STM32_GPIO_AF12,
+	STM32_GPIO_AF13,
+	STM32_GPIO_AF14,
+	STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+	enum stm32_gpio_port	port;
+	enum stm32_gpio_pin	pin;
+};
+
+struct stm32_gpio_ctl {
+	enum stm32_gpio_mode	mode;
+	enum stm32_gpio_otype	otype;
+	enum stm32_gpio_speed	speed;
+	enum stm32_gpio_pupd	pupd;
+	enum stm32_gpio_af	af;
+};
+
+struct stm32_gpio_regs {
+	u32 moder;	/* GPIO port mode */
+	u32 otyper;	/* GPIO port output type */
+	u32 ospeedr;	/* GPIO port output speed */
+	u32 pupdr;	/* GPIO port pull-up/pull-down */
+	u32 idr;	/* GPIO port input data */
+	u32 odr;	/* GPIO port output data */
+	u32 bsrr;	/* GPIO port bit set/reset */
+	u32 lckr;	/* GPIO port configuration lock */
+	u32 afr[2];	/* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+	struct stm32_gpio_regs *regs;
+};
+
+static inline unsigned stm32_gpio_to_port(unsigned gpio)
+{
+	return gpio / 16;
+}
+
+static inline unsigned stm32_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 16;
+}
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h
new file mode 100644
index 0000000..9ff1f13
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32h7/stm32.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/*
+ * This empty files is needed to not break compilation
+ * Some common drivers to STM32F4/F7 and H7 include a stm32.h file
+ * Some cleanup need to be done to communalize all the following
+ * stm32.h files:
+ *
+ * arch/arm/include/asm/arch-stm32f1/stm32.h
+ * arch/arm/include/asm/arch-stm32f4/stm32.h
+ * arch/arm/include/asm/arch-stm32f7/stm32.h
+ */
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 947ce5f..b618b60 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -25,7 +25,24 @@
 	select SPL_SYS_MALLOC_SIMPLE
 	select SPL_XIP_SUPPORT
 
+config STM32H7
+	bool "stm32h7 family"
+	select CLK
+	select DM_GPIO
+	select DM_RESET
+	select MISC
+	select PINCTRL
+	select PINCTRL_STM32
+	select RAM
+	select REGMAP
+	select STM32_SDRAM
+	select STM32_RCC
+	select STM32_RESET
+	select STM32X7_SERIAL
+	select SYSCON
+
 source "arch/arm/mach-stm32/stm32f4/Kconfig"
 source "arch/arm/mach-stm32/stm32f7/Kconfig"
+source "arch/arm/mach-stm32/stm32h7/Kconfig"
 
 endif
diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile
index 6b76944..0f5ac37 100644
--- a/arch/arm/mach-stm32/Makefile
+++ b/arch/arm/mach-stm32/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_STM32F4) += stm32f4/
 obj-$(CONFIG_STM32F7) += stm32f7/
+obj-$(CONFIG_STM32H7) += stm32h7/
diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig
new file mode 100644
index 0000000..55e6217
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32h7/Kconfig
@@ -0,0 +1,12 @@
+if STM32H7
+
+config TARGET_STM32H743_DISCO
+	bool "STM32H743 Discovery board"
+
+config TARGET_STM32H743_EVAL
+	bool "STM32H743 Evaluation board"
+
+source "board/st/stm32h743-eval/Kconfig"
+source "board/st/stm32h743-disco/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32/stm32h7/Makefile b/arch/arm/mach-stm32/stm32h7/Makefile
new file mode 100644
index 0000000..97f92f7
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32h7/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2017
+# Patrice Chotard <patrice.chotard@st.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += soc.o
diff --git a/arch/arm/mach-stm32/stm32h7/soc.c b/arch/arm/mach-stm32/stm32h7/soc.c
new file mode 100644
index 0000000..a65fab6
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32h7/soc.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m_mpu.h>
+
+u32 get_cpu_rev(void)
+{
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	int i;
+
+	struct mpu_region_config stm32_region_config[] = {
+		/*
+		 * Make all 4GB cacheable & executable. We are overriding it
+		 * with next region for any requirement. e.g. below region1,
+		 * 2 etc.
+		 * In other words, the area not coming in following
+		 * regions configuration is the one configured here in region_0
+		 * (cacheable & executable).
+		 */
+		{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+		O_I_WB_RD_WR_ALLOC, REGION_4GB },
+
+		/* Code area, executable & strongly ordered */
+		{ 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW,
+		STRONG_ORDER, REGION_8MB },
+
+		/* Device area in all H7 : Not executable */
+		{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
+		DEVICE_NON_SHARED, REGION_512MB },
+
+		/*
+		 * Armv7m fixed configuration: strongly ordered & not
+		 * executable, not cacheable
+		 */
+		{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
+		STRONG_ORDER, REGION_512MB },
+	};
+
+	disable_mpu();
+	for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+		mpu_config(&stm32_region_config[i]);
+	enable_mpu();
+
+	return 0;
+}
+
+void s_init(void)
+{
+}